In integrated circuits which utilize field-effect transistors, it is often desirable to accurately determine the voltage threshold (V.sub.T) of the individual devices. For example, neural networks typically require frequent measurement of FET voltage thresholds as part of the learning or training process. A great deal of time is routinely spent in measuring the voltage threshold of these devices in order to properly set synapse weights on floating gate devices to obtain a rapidly converging response for the network. At present, there is no way to quickly obtain an accurate and precise measurement of the V.sub.T of each of the various floating gate transistors within a neural network array.
The traditional method of measuring V.sub.T involves gradually ramping the gate voltage of the device-under-test (DUT) while simultaneously monitoring the current flow through the channel of the device. The voltage threshold is arbitrarily defined as the gate to source voltage at which a predetermined current flows across the channel region. Usually, the voltage threshold is defined as the gate voltage which produces approximately one microampere of current flow between the source and drain regions. Once this predetermined current is reached (e.g., about 1 .mu.A), ramping of the gate voltage is halted and the threshold voltage is recorded.
Depending on the resolution required, the ramping method normally takes an inordinate amount of test time due to the small increments or steps in voltage which are required. Performing a binary search helps to reduce the number of testing points. But binary searching typically requires the use of expensive digital to analog (D/A) converters which transform the digital binary sequence into a gate voltage. Moreover, D/A converters have their own speed-limitations so that the overall reduction in test time using the binary method is not overly significant. D/A converters take up a lot of silicon area and are difficult to integrate with other circuitry.
Other past approaches include attempts to automate the testing process utilizing an operational amplifier coupled to the DUT through a feedback network. The main problem associated with this technique is the fact that the feedback loop often includes a path through the decoding circuitry of the semiconductor memory array. Because the decoding circuits have their own associated resistances and capacitances, these types of automated circuits exhibit a tendency to oscillate unless the response (e.g., gain) of the operational amplifier is weakened considerably. Slowing of the operational amplifier's response, of course, slows down the entire testing procedure. The effect of a weakened response is usually dramatic enough that most automated circuits perform no better than conventional linear or step ramp approaches.
Thus, there exists an unrequired need for a circuit capable of obtaining rapid voltage threshold measurements on field-effect devices fabricated in an integrated circuit. The present invention provides a circuit which can make fast and accurate threshold voltage measurements on semiconductor FET devices. The invention is ideally suited for use in measuring the V.sub.T of devices formed as part of a large array in an integrated circuit. In addition, the invented circuit can be easily fabricated as an integral part of the semiconductor circuit which contains the transistors to be tested. This obviates the need for an external ramp generator binary sequence generator, or other external measurement equipment.